試題詳解

1. A software engineer is optimizing a real-time embedded system. The processor being used follows the RISC architecture. Which of the following optimizations is best suited for this processor?
(A) Minimizing pipeline stalls by keeping instruction execution times uniform
(B) Using highly optimized microcode for complex instructions
(C) Utilizing variable-length instructions to reduce code size
(D) Optimizing for micro-op fusion to minimize instruction count
(E) Relying on Instruction-Level Parallelism (ILP) to reduce execution cycles