申論題

(Problem 5](20%) Design an asynchronously resettable positive edge-triggered finite state machine that has two one-bit input a and b, and one output y. y equals I if a = b during any five cycles. Otherwise, y equals 0. For example, 

(a) Give Verilog/VHDL codes of an asynchronously resettable positive edge-triggered flip-flop. (3%)