試題詳解

複選題
3. Which of the following statements are true regarding the pipeline hazards of a 5-stage MIPS CPU?
(A)The data forwarding technique passes data to the previous instructions that need the data
(B) The structural hazard happens when a required resource is busy
(C) Rearranging the instructions may solve some of the data hazards
(D)If we put the register comparator and the target address calculator at the ID stage, then 2 stalls are needed for a branch hazard
(E) If we put the register comparator and the target address calculator at the ID stage, and a comparison register is a destination of immediately preceding load instruction, then 1 stall is needed