複選題

1. Consider a computer running a program with CPU times shown in the following table:

(A) If the time for FP instructions is reduced by 40%, the total execution time of the program reduced in percentage is 20%.
(B) If the time for L/S instructions is reduced by 80%, the speedup of the program is 1.25.
(C) If the speed of the INT instructions is improved to 3 times faster, this program may run 1.25 times faster.
(D) This program may run 1.8 times faster by improving the speed of FP instructions.

複選題2.Which of the following statements are correct? (A) The dynamic power dissipation of CMOS is proportional to the square of the voltage applied. (B) Static power dissipation occurs because of leakage current that flows even when a transistor is off. (C) Computers at lower utilization use less power proportionally. (D) The main reason for the switch from high-performance uniprocessors to multiprocessors with simpler cores and lower clock rates in recent years is the power limit.

複選題3. Given the IEEE-754 single precision floating-point operand format as follows, (A) The decimal number -13.5 is represented as 1 10000011 11011000000000000000000 (B) The largest positive normalized number is (C) The smallest positive denormalized number is (D) Exponents with all 1's are reserved for ±∞ and NaN (Not a Number).

複選題4. Multiply algorithm (A) For a multiplication with multiplier 1100101111100111, the traditional multiplication algorithm performs 11 additions for the product. (B) For a multiplication with multiplier 1100101111100111, Booth's algorithm performs 3 additions and 3 subtractions for the product. (C) Booth's algorithm requires less arithmetic operations than that of the traditional multiplication algorithm. (D) Booth's algorithm may be applied to two's complement multiplication.

複選題5.Which of the following statements are correct? (A) For a fixed-size cache, miss rate will decrease as the block size increases. (B) Increasing block size can decrease compulsory miss. (C) For a two-level cache, the design of the primary (first-level) cache focuses on minimizing its miss rate, and the design of the second-level cache focuses on minimizing its hit time. utilizes (D) Fetching instructions in a loop temporal locality while sequential instruction access demonstrates spatial locality.

複選題6. What instruction(s) below may fail to run correctly if the datapath labeled A in the single-cycle CPU figure has been cut ? (A) add (B) sw (C)lw (D) slt

複選題7. What instruction(s) below may fail to run correctly if the control signal "RegDst" in the single-cycle CPU has been cut and stuck at 1? (A) add (B) sw (C) lw (D) slt

複選題8. With single-cycle CPU, what control signal(s) below will be set to 1 when the code runs to the cycle? (A) RegDst (B) ALUSrc (C) MemToReg (D) Mem Write

複選題9. With the pipelined CPU, what control signal(s) below will be set to 1 when the code runs to the cycle? (A) RegDst (B) ALUSrc (C) MemToReg (D) Mem Write

10. With the pipelined CPU, what control signal below will be set to 1 when the code runs to the cycle? (A) RegDst (B) ALUSrc (C) MemToReg (D) Mem Write

101年 - 101 國立交通大學_碩士班考試入學試題_資訊聯招：計算機組織#105750