17. Consider the following instruction mix for a processor:

 ALU operations: 40%, uses 4 cycles. 

Branch operations: 30%, uses 4 cycles. 

Memory references: 30%, uses 5 cycles. 

The un-pipelined processor has a clock cycle time of 1 ns. The pipelined processor has a clock cycle time of 1.2 ns. Suppose that we ignore any latency and hazards, and assume that the pipelined processor has an ideal CPI (cycles per instruction) of 1. How much speedup can be achieved when comparing the un-pipelined processor and the pipelined processor?
(A) 3.28
(B) 3.35
(C) 3.58
(D) 3.86
(E) 3.98