2. A processor has a four-way set associative L1 data cache of 8 KByte in size, with 64-byte cache blocks. The physical address is 32 bits and data addresses are to the byte. How many bits will be for the tag field?
(A) 18
(B) 19
(C)20
(D) 21
(E) 22

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統計： A(0), B(0), C(0), D(1), E(0) #2789104