申論題

16. (5 points) Continuing from the last question, please answer which of the following statements is/are correct?

(a) Suppose that the RS is empty and the front end (decoder/register-renamer) will continue to supply two new instructions per clock cyclc. In cycle 0, the first two register-renamed instructions of this sequence appear in the RS. Assume it takes one clock cycle to dispatch any op in addition to the functional unit latencies. Then 9 clock cycles are required in the first iteration of this code sequence.