申論題

7.(25 pts) Consider a 5-stage (IF, ID, EX, MEM, WB) RISC-V pipelined processor (Figure 1) composed of logic blocks with the following latency (any unspecified block latency is treated as O):

(b)( 5 pts) When the first instruction (tw) is in the MeM stage, which instructions are executing in the ID (b1) and EX (b2) stage?

(請填寫instructionnumber不要instruction)