申論題

(Problem4] (15%) Design an asynchronously resettable positive edge-triggered counter with the following repeated binary sequence: 0, 3, 1, 4, 7, 5, 2, 6. Note that the counter must have the parallel- load capability, ie, the content of the counter can be arbitrarily specified via the circuit inputs.

(b) Write RTL Verilog/VHDL codes to implemnent the counter. (10%)