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5. (8%) A processor and two options for improving its hardware and compiler design are described as follows:

相關申論題

(1) Is it possible to use one single branch-on-equal (beq) MIPS instruction to get to address 0x0003 0000?

(2) Same to question (a) except that the address is changed to Oxffff ff00.

(3) Is it possible to use one jump (j) MIPS instruction to get to address 0x0003 0000?

(4) Same to question (c) except that the address is changed to Oxffff ff00.

(1) The pipelined CPU for which assume the forwarding mechanism has been designed and the branch outcome is determined at MEM stage.

(2) The pipelined CPU for which assume the forwarding mechanism has been designed and some hardware has been added to determine the branch outcome at ID stage.

(1) Which one(s) cannot have "small writes" to occur in parallel?

(2) Which one(s) cannot have "small reads" to occur in parallel?

(3) Which one has the best "small reads" latency?

(4) Which one is least tolerant to disk failure?

相關試卷

101年 - 101 國立交通大學_碩士班考試入學試題_資訊聯招：計算機組織#105750

101年 · #105750

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