(2) Report the result status in sign, zero, overflow, and carry bits.

題組內容

[Problem 4] (20%) Given the 8-bits adder ( named Add8), the 2-to-1 8-bits multiplexers (named MUX8 _2to1) and the basic gates such as NOT, AND, OR, NAND, and NOR, you are asked to design an ALU in function block diagrams, which must match the following requirements:

[Problem 5] Use the following code fragment:Loop: Assume the initial value of R3 is R2+200. Use the five-stage instruction pipeline ( IF, DEC, EXE, MEM, WB) and assume all memory accesses are one cycle operation. Furthermore, branches are resolved in MEM. Show the timing of this instruction sequence for the five-stage instruction pipeline with normal forwarding and bypassing hardware. Assume that branch is handled by predicting it has not taken. How many cycles does this loop take to execute? (10%) Assuming the five-stage instruction pipeline with a single-cycle delayed branch and normal forwarding and bypassing hardware, schedule the instructions in the loop including the branch- delay slot. You may reorder instructions and modify the individual instruction operands, but do not undertake other loop transformations that change the number of op-code of instructions in the loop. Show a pipeline timing diagram and compute the number of eyeles needed to execute the entire loop. (15%

題組內容

(2) Report the result status in sign, zero, overflow, and carry bits.

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