(2) Same to question (a) except that the address is changed to Oxffff ff00.

(1) Is it possible to use one single branch-on-equal (beq) MIPS instruction to get to address 0x0003 0000?

(3) Is it possible to use one jump (j) MIPS instruction to get to address 0x0003 0000?

(4) Same to question (c) except that the address is changed to Oxffff ff00.

(1) The pipelined CPU for which assume the forwarding mechanism has been designed and the branch outcome is determined at MEM stage.

(2) The pipelined CPU for which assume the forwarding mechanism has been designed and some hardware has been added to determine the branch outcome at ID stage.

(1) Which one(s) cannot have "small writes" to occur in parallel?

(2) Which one(s) cannot have "small reads" to occur in parallel?

(3) Which one has the best "small reads" latency?

(4) Which one is least tolerant to disk failure?

4. (8%) Assume the system workload consists of repeated reads of 64KB block at random disk locations. For the following system setup, (A) what is the IOPS (I/Os per second) for CPU, memory bus, and disk drive,respectively? (B) what (CPU, memory bus, or disk) is the bottleneck in the system?●The user program uses 2 million cycles to process each I/O operation.●The operating system requires 1 million cycles of overhead for each I/O operation.●The clock rate is 3GHz.●The maximum sustained transfer rate of the memory bus is 640MB/sec●One disk drive which rotates at 7200RPM, has an average seek time of 8ms, and has a transfer rate of 64MB/sec. The disk controller overhead is 2ms.Express your answer as the following table

101年 - 101 國立交通大學_碩士班考試入學試題_資訊聯招：計算機組織#105750