Fig. 3 6. Design the circuit of Fig. 4 for an enhancement MOSFET having Vt = 2 V and k'n(W/L) = 2 mA/V2. Let VDD = VSS = 10 V. (a) Design for the largest possible “RD” (for a dc bias current of 1 mA and for the largest possible voltage gain consistent with allowing a 2-V peak-to-peak voltage swing at the drain.) (10%)