申論題內容
(b) [3%] If the processor has a base CPI of 1, and clock rate of 4 GHz. Assume the memory
access time is 100 ns, including al the miss handling. Suppose the miss rate per instruction
at the primary cache is 3%. Now we add a secondary data cache that has a 5 ns access time
for either a hit or a miss, and is large enough to reduce the miss rate to main memory to
0.5%. What is the total CPI of this two-level cache?
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