申論題

(Problem 2](18%) Design a synchronously resettable positive edge-triggered finite state machine that has a one-bit input d and two outputs x and y. x should be 1 if d has been 0 for at least two cycles (not necessarily consecutively). y should be 1 if d has been O for at least three consecutive cycles. For example, the input sequence d=0101100011010 results in the output x=0011111111111 and the output y=0000000100000.

(c)Write RTL Verilog/VHDL codes to implement the finite state machine you designed in (b). (10%)