(c) What is a Mealy finite state machine? (2%) Give one design example of a Mealy finite state machine. Note that you need to give the function of this design and its state diagram. (5%)

(a) Give one example to show that "the simplest expression of a Boolean function may not be unique". (4%)

(b) Give a general structure of a sequential circuit and use this structure to explain the differences of a sequential circuit from a combinational circuit (4%)

(d)Give some waveforms to explain the meaning of the setup time and the hold time of a D flip-flop. (5%)

(a)Give Verilog/VHDL codes of a synchronously resettable positive edge-triggered flip-flop. (3%)

(b) Draw the state transition diagram and define each state clearly. (5%)

(c)Write RTL Verilog/VHDL codes to implement the finite state machine you designed in (b). (10%)

[Problem 3] (15%) 2-4-2-1 is a useful 4-bit binary code to represent decimal digits, as listed in Table 1. Design a combinational circuit F that can check if the decimal input encoded by 2-4-2-1 is a prime number, i.e., a positive integer that is greater than 1 and can be exactly divided by only 1 and itself. That is, the output F of the circuit equals 1 if and only if the decimal input is a prime number. You need to show the truth table of this circuit and design the two-level NAND-NAND network using the minimumn number of logic gates and literals. Please note that the input code words (w, x, y, z) and their complements can be used directly as fan-in in the final logic diagram, and the unused input code words can be used as don't care conditions for logic simplification.

(a) Draw the state transition diagram and define each state clearly. (5%)

(b) Write RTL Verilog/VHDL codes to implemnent the counter. (10%)

(a) by using only NOR and inverter gates. (5%)

103年 - 103 國立中山大學_碩士班招生考試_電機系(己組)：數位電路#110032

102年 - 102 國立中山大學_碩士班招生考試_電機系(丙、己組)：數位電路#110045