109年 - 109 國立中山大學_碩士班招生考試_資工系(甲、乙組)：計算機結構#105754

7. A byte-addressable processor is connected to a single memory channel that has a single
rank of DRAM. The physical address space is 32 bits, and the processor uses the following mapping shown in Table 3, to index the DRAM. Each DRAM row has a certain number of columns, where a
column has the same size of a cache line. The processor uses 64-byte cache lines. The Columns is 6
bits and the Cache Line Offset is also 6 bits. In addition, the row size is 4 KB.
Table 3 Mapping from the physical address to DRAM

Table 4 shows the memory request queue that has 4 pending memory request at time 0.
Assuming that
A row buffer hit takes 50 cycles

A row buffer conflict takes 250 cycles.
Requests going to different banks can be processed by the banks in parallel.

All the row buffers are closed at times 0.
The controller cannot issue two requests at the same time. Each request takes 10 cycles to process,
so it takes 10 cycles between issuing two separate requests to the memory.

The controller employs First Ready-First Come First Serve (FR-FCFS) scheduling policy.
Table 4. the state of the memory request queue at time 0.

If it takes 320 cycles to finish processing all four requests in the memory, at least how many banks does this rank of DRAM have?