1.1 (2%) A computer has 128MB of memory. Each word in the computer is eight bytes. How many bits at least are needed to address any single word in memory?
(A) 8 bits
(B) 16 bits
(C) 24 bits
(D) 32 bits

1.2 (2%) In modern computer architectures, TLB is usually involved to improve the efficiency of the memory hierarchy. If we meet a situation of TLB miss, what is the following description true? (A) The data requested by the CPU must be not in the cache. (B) The data requested by the CPU must be not in the main memory. (C) The CPU is failed to get the physical address of the required data. (D) The CPU must send a request to access the main memory immediately.

1.3 (2%) To solve the cache coherence problem, Snoopy protocol is the simplest. Regarding the Snoopy coherence protocol, what is the following description true? (A) Any CPU should invalidate the cache block if it receives a write miss signal to the data in the local cache block from the bus. (B) Any CPU should invalidate the cache block if it receives a read miss signal to the data in the local cache block from the bus. (C) The Snoopy coherence protocol is an atomic operation. (D) The Snoopy coherence protocol is proper to apply to a single-core system.

1.4 (2%) Regarding the cache miss, what is the following description true? (A) Compulsory miss indicates that the cache cannot contain all blocks required for the execution. (B) Coherence miss only happens in multi-core systems. (C) The miss rate will go down while the block size is made very large. (D) Increasing the associativity decreases miss rate due to lower compulsory miss.

1.5 (2%) Regarding the cache design, what is the following description true? (A) With the criteria of the identical entries, we need more tag bits in a multi-word cache than in set-accusative cache. (B) Through interchanging the loops in a code, the cache miss rate cannot be degraded. (C) Through the way prediction technique, the miss penalty during the cache access can be reduced. (D) If we pipeline the cache access, the cache bandwidth can be improved.

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