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103年 - 103 國立中山大學_碩士班招生考試_資工系(甲、乙組):計算機結構#105837
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題組內容
7. Assume that you are using a standard 5-stage pipelined processor (as shown in Problem 6) to execute the following MIPS instructions:
lw $1,40($6)
dd $6,$2.$2
sw$6,50($1)
(a) Indicate dependences and their type.
其他申論題
(b) What is the clock cycle time if we only have to support LW (load word) instructions?
#450989
(e) What is the clock cycle time if we must support ALU, branch, load/store instructions? (Hint: You need to find the overall latencies of the blocks in the longest path required to execute an instruction.)
#450990
(a) What is the clock cycle time in a pipelined and non-pipelined processor?
#450991
(b) What is the total latency of an LW instruction in a pipelined and non-pipelined processor? (5%)
#450992
(b) Assume there is no forwarding in this pipelined processor. Indicate hazards and add NOP instructions to eliminate them.
#450994
(a) Consider a direct-mapped cache with 16KB of data and 16-byte blocks, assuming a 32-bit 300ps address. What is the length of the tag field? How many total bits are required, assuming a valid bit is used?
#450995
(b) Assume an instruction cache miss rate for gcc of 2% and a data cache miss rate of 4%. If a machine has a CPI of 2 without any memory stalls and the miss penalty is 40 cycles for all misses, determine how much faster a machine would run with a perfect cache that never missed. Assume 36% of instructions are loads/stores.
#450996
(a) Page fault
#450997
(b) Direct memory access (DMA)
#450998
1. Use Laplace Transform to solve the differential equation y"+4y'+3y=e';y(0)=0,y'(0)=2.
#450999