4. (15%) For a static four-input NAND gate with L a 0.18 um, all transistor sizes are chosen to match the delay of a basic CMOS inverter with (W/L)n = n and (W/L)p= p.
申論題內容
(c) (4%) For the static four-input NAND gate, find the ratio of the maximum to minimum current
available to (a) charge a load capacitance and (b) discharge a load capacitance.
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