題組內容

5. (25%) Design the circuit in Figure 4 to obtain a de vottage of +0.1 V at each of the drains of Q1and Q2 when6142ba001d2ad.jpg. Operate all transistors at6142ba2198f78.jpg and assume that for the process technology in which the circuit is fabricated, 6142ba48ccec6.jpg. Neglect channel- length modulation.
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(d) (5%) What are the lower and upper limits of the input common-mode voltages?