2.1 (10%) What is the CPI if this single-core processor only has one level of cache?

題組內容

2. (30%) Suppose we have a processor with a base CPI of 1.0, assuming all reference hit in the primary cache, and a clock rate of 5GHz. Assume a main memory access time of 100 ns, including all the miss handling. Suppose the miss rate per instruction at the primary cache is 2%.

4.3 (20%) Without considering the data transferring time, we assume the access time of L2 cache is 5 ns including all the miss handling； the access time of the main memory is 100 ns including all the miss handling； the access time of the hard disk is 1 us including all the miss handling. According to the data transference time between each memory level, we ignore the data transference time between the L1 and L2 cache and the data transference time between the main memory and the lowest level cache and disk are both 50 ns ineluding all the miss handling. In this system, the TLB will be located at the lowest level cache. When a data request comes, the TLB must be accessed first. If the TLB miss happens, we need to spend ions to handle the TLB-miss exception. When we adopt direct mapping strategy, the miss rate of the L1 cache and the embedded TLB are both 2%； the miss rate of the L2 cache and the embedded TLB are both 0.5%. If the 2-way mapping strategy is applied, the miss rate of the L1 cache and the embedded TLB are both 1%； the miss rate of the L2 cache and the embedded TLB are both 0.1%. At last, the miss rate of the main memory is 0.1%. During manufacturing, we need to spend 0.01 USD to handle one bit in each kind of memory. Please provide a design suggestion, including how many cache level you suggest and what kind of mapping strategy for each cache level you suggest, to your customer by considering the system performance and the manufacturing simultaneously cost.

題組內容

2.1 (10%) What is the CPI if this single-core processor only has one level of cache?

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