申論題

3. A standard pipelined CPU contains five pipeline stages: instruction fetch (IF), instruction decode (ID), ALU execution (EX), memory access (MA), and result write-back (WB). Assume that the critical path delays of the five types of instruction operations IF, ID, EX, MA, WB are 20ms, 20ns, 50ns, 40ns, 30ns respectively.

3.2 Assume that a computation task contains only 100 instructions and there is no hazard for these instructions, what is the throughput of this task? What is the total latency of finishing executing this task? What is the average cycle per instruction (CPI) in this task?