3.3 Provide two reasons why a superscalar microarchitecture could provide higher performance than a "same-width" VLIW microarchitecture?

1.2 Based on your design, if you could halve the cycle latency of any single category of instruction, but at the cost of increasing the cycle time by 20%. Should you make this change, and if so, what category of instruction should you speed up? (load, store, branch, add, or divide)