申論題

4. Compare the single-cycle implementation, in which all instructions take 1 clock cycle, with the five-stage (IF, ID, EX, MEM, WB) pipelined implementation using the following eight instructions: load word (Iw), store word (sw), subtract (sub), and (and), or (or), set-less-than (slt) and branch-on-equal (beq). The operation times for the major functional units are 2 ns for memory access, 2 ns for ALU operation, and 1 ns for register file read or write.

4.2 What is the clock cycle time for the single-cycle implemmentation and the pipelined implementation? Please copy Table 4-2 to your answer sheet and fi1l in the blanks with your answers.