(b) Optimize the hardware. The hardware team claims that it can improve the processor design to
give it a clock rate of 600 MHz. Call this machine Mopt.
The following measurements have been made using a simulator for Mbase and Mopt.

What are the CPI and MIPS (million instructions per second) rate for Mbase and Mopt? Copy Table
1-1 to your answer sheet and fill in the blanks with your answers.

(a) Leave the design as it stands. Call this base machine Mbase. It has a clock rate of 500 MHz.

1. You are the lead designer of a new processor. The processor design and compiler arecomplete, and now you must decide whether to produce the current design as it stands or spendadditional time to improve it. Please consider and answer the following problems.1.2 The compiler team proposes to improve the compiler for the machine to further enhanceperformance. Call this combination of the improved compiler and the base machine Mcomp. Theinstruction improvements from this enhanced compiler have been estimated as follows.Instruction class Percentage of instruction executed vs. base machineFor example, if the base machine executed 500 class A instructions, Mcomp would execute 0.9 x500 = 450 class A instructions for the same program. What is the CPI for Mcomp? How much fasteris Mcomp than Mbase? Copy Table 1-2 to your answer sheet and fill in the blanks with your answers.

2. Here is a loop in C:Assume that A is an array of 100 elements and the variables g, h, i, and j are in registers $s1, $s2,$s3, and $s4, respectively. In addition, assume that the base of the array A is in $s5. Other registersthat can be used are $tO and $t1. A possible MISP assembly code corresponding to this C loop isshowed as follows:Please determine proper values for the operands (OPA, OPB, OPC, OPD, OPE). Copy the Table 2 toyour answer sheet and fill in the operand values.

3. Figure 1 shows a 16-bit adder consisting of four 4-bit ALUs using carry lookahead. Assume that gi = ai bi (generate) and pi = aitbi (propagate). Determine the value of P0, P1, P2, P3, G0, G1, G2, G3, and C4 (CarryOut) when adding two 16-bit numbers 0001 1010001 1001 1 and 1110010111101011 with Carry_ In bit equal to 0. Please copy Table 3 to your answer sheet and fill in the blanks with your answers.

4.1 Please complete the Table 4-1 by filling in the time for each component to calculate the total time of each instruction executed in the single-cycle implementation. Assume that the multiplexors, control unit, PC accesses, and sign extension unit have no delay. Please copy Table 4-1 to your answer sheet and fill in the blanks with your answers.

4.2 What is the clock cycle time for the single-cycle implemmentation and the pipelined implementation? Please copy Table 4-2 to your answer sheet and fi1l in the blanks with your answers.

4.3 Consider a program consisting of 100 1w instructions and in which each instruction isdependent upon the instruction before it. What would the actual CPI be if the program were run on the single-cycle implementation and the pipelined implementation with a forwarding unit and a hazarddetection unit? Please copy Table 4-2 to your answer sheet and fill in the blanks with your answers.

5. Increasing associativity requires more comparators, as well as more tag bits per cache block. Assuming a cache of 4K blocks, a four-word block size, and a 32-bit address, find the total number of sets and the total number of tag bits for caches that are direct mapped, two-way and four-way set associative, and fully associative. Please copy Table 5 to your answer sheet and fill in your answers.

6. Here is a series of address references given as word addresses: 1, 4, 8, 5, 20, 17, 19, 56,9, 11, 4, 43, 5, 6,9, 17. Assuming a direct-mapped cache with four-word blocks and a total size of 16 words that is initially empty, label each reference in the list as a hit or a miss and show the final contents of the cache. Please copy Table 6-1 and Table 6-2 to your answer sheet and fill in your answers.

7. Suppose we have a processor with a base CPI of 1.0, assuming all references hit in the primary cache, and a clock rate of 1 GHz. Assume a main memory access time of 100 ns, including all the miss handling.

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