4.1 How nuny bits in toteal (including the tag bits and vaid bite) are reqvired for dlue tt aor cache with 16K bytes of data and 16-byte blocks, assuming a 32-bit address and one valid bit for each cache block?
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4.7 Suppose that in 1000 memory references, there are 40 misses in the first-level cache and 20 misses in the second-1 level cache. Assume the miss pen nalty from L2 cache to memo ory is 200 clock cycles, the hit time of L2 cache is 10 clock cycles, and the hit time of Ll cache is 1 clock cycle. What is the average memory y access time? Hint: average memory access time = LI_hit_time + Ll miss rate * ( 12 hit time + L2 local_miss_rate * * L2 miss penalty ) where the 12 local miss_rate is the nunber of misses in L2 cache divided by the total numnber of memory accesses to L2 cache.
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