4.1 How nuny bits in toteal (including the tag bits and vaid bite) are reqvired for dlue tt aor cache with 16K bytes of data and 16-byte blocks, assuming a 32-bit address and one valid bit for each cache block?
申論題內容
4.8 Continued with the previous problem, and assuming that there is 1.5 memory references per
instruction, what are the average stall cycles per instructions? Hint: average memory stall pet
instruction = Ll_misses _per_instruction L2 hit time + L2 misses per _instruction
12 _miss_penaity
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