申論題

7. Consider three processors with different cache configurations:
Cache 1: Direct-mapped with two-word blocks
Cache 2: Direct-mapped with four-word blocks
Cache 3: Two-way set associative with four-word blocks
The following miss rate measurements have been made:
Cache 1: Instruction miss rate is 3.75%； data miss rate is 5%
Cache 2: Instruction miss rate is 2%； data miss rate is 4%
Cache 3: Instruction miss rate is 2%: data miss rate is 3%
For these processors, one-half of the instructions contain a data reference. Assume that the cache
miss penalty is 6 + Block size in words. The CPI for this workload was measured on a processor with
Cache I and was found to be 2.0.