(b) [4%] Why do we need valid bits and dirty bits in cache designs?

(d) [12%] For a cache with 8 blocks, given the following reference addresses.1, 74, 39, 28, 21, 5, 7, 39, 20, 33, 1, 21Identify the index and tag for these references of a direct mapped cache, a 4-way set associative cache and a fully associative cache, respectively. Also, explain if each reference is a hit or a miss, assuming the cache is initially empty and the least recently used block replacement policy is assumed.

題組內容

(b) [4%] Why do we need valid bits and dirty bits in cache designs?

相關申論題

相關試卷