109年 - 108 國立中山大學_碩士班招生考試_電機系(己組)：計算機結構#124091

1. [20%] Translate the following C code to the minimum MIPS assembly instructions
int A[20], B[20]；
i=0；
while (A[i]!=0 && i＜20){
B[i] = A[i]+B[A[i]]+i；
i++；
}
At the beginning of this code segment, the only values in registers are the base address of arrays A and B in registers $al and $a2. Assume that the value of i is stored in the register $t1.

(a) (6%) We can use the execution time of programs to evaluate performance of a processor design.
Give equation(s) to explain how to formally calculate the execution time of a given program for a target processor.

(b) (3%) For the MIPS program you wrote in Problem 1, assume the program is run with a MIPS processor with 200MHz clock rate. Below is the number of cycles for each type of instructions.
In the worst case, how many ms (micro seconds) will the processor take to run your program?

(c) (6%) Give at least three strategies that we can use for a MIPS processor design to enhance its performance and explain how.

(a) (4%) Given a single precision IEEE 754 bit stream S: 1 01111101 00100000000000000000000.
What does this floating number mean? Write your final answer with decimal expression.

(b) (6%) Give definitions and examples of "overflow" and "underflow" for floating-point representation.

(c) (5%) Multiply S and x (x=238.0625), and represent the result using IEEE 754 single precision
format. Also describe if overflow or underflow occurs.

(a) (5%) Which existing blocks (if any) can be used for this instruction?

(b) (5%) Which new functional blocks (if any) do we need for this instruction?

(c) (5%) What new signals do we need (if any) from the control unit to support this instruction?

(d) (5%) Give the values of all the required control signals when the LRA instruction is executed.

(a) [6%] What are direct-mapped cache, set-associative cache and fully associative cache?

(b) [4%] Why do we need valid bits and dirty bits in cache designs?

(c) [8%] Draw the architecture of a direct-mapped cache with 4 blocks and explain how this cache works as detailed as possible.

(d) [12%] For a cache with 8 blocks, given the following reference addresses.
1, 74, 39, 28, 21, 5, 7, 39, 20, 33, 1, 21
Identify the index and tag for these references of a direct mapped cache, a 4-way set associative cache and a fully associative cache, respectively. Also, explain if each reference is a hit or a miss, assuming the cache is initially empty and the least recently used block replacement policy is assumed.