3. A multicycle CPU has three implementations. The first one is a 5-cycle IF-ID-EX- MEM-WB design running at 4.8GHz, where load takes 5 cycles； store/R-type 4 cycles and branch/jump 3 cycles. The second one is a 6-cycle design running 5.6GHz, with MEM replaced by MEM1 and MEM2. The third is a 7-cycle design running at 6.4GHz, with IF further replaced by IF1 and IF2. Assume we have an instruction mix: load 26%, store 10%, R-type 49%, branch/jump 15%.