申論題內容
6.3 If the cache access time determines the processor's clock cycle time, which is often the case,
AMAT may not correctly indicate whether one cache organization is better than another. If the
processor's clock cycle time must be changed to match that of a cache, is this a good tradc-off?
Assume the processors are identical except for the clock rate and the number of cache miss cycles;
assume 1.5 references per instruction and a CPI without cache misses of 2. The miss penalty is 20
cycles for both processors.