題組內容

6. Let the above datapath be implemented with pipelining. Assume that individual stages of the datapath (Insrtuction Fetch, Instruction Decode, Execution, Memory access, Write Back) have the following latencies: 61e614f9efa27.jpg

(b) What is the total latency of an LW instruction in a pipelined and non-pipelined processor? (5%)