.1.3 Virtual memory typically uses a write-back strategy, rather than a write-through

1.4 If the cycle time and the CPI both increase by 10% and the number of instruction decreases by 20%, then the execution time will remain the same.

1.5 In uniform memory access (UMA) designs, all processors use the same address space. 

2.2 How much power saving would be achieved by placing 60% of the servers in the "barely alive state?

3.1 Do you think it is worthwhile to go for the 6-cycle design over the 5-cycle design?

3.2 How about the 7-cycle design over the 6-cycle design, is it worthwhile?

4. Identify all of the data dependencies in the following code running in a 5-stage pipelined MIPS CPU. Which dependencies are data hazards that will be resolves via forwarding? Which dependencies are data hazards that will cause a stall? strategy.

5.1 Determine the tag size for each block.

5.2 Assume each block requires 2 extra valid bits. What is the size of the cache memory?

6. Given the following datapath for the single-cycle implementation of a computer and thedefinition of its instructions:Assume that the instructions are fixed length and the operation time for the major functional units inthis implementation are as follows:●Memory units: 2ns●ALU and adders: 2ns●Register file (read or write): 1ns●Multiplexers, control unit, PC accesses, sign extension unit, and wires: no delay Please compute the required time for each instruction and explain why.

7. The following series of branch outcomes occurs for a single branch in a program. T means the branch is taken； N means the branch is not taken. TTTNNTTT How many instances of this branch instruction are mis-predicted with a 1-bit and 2-bit local branch predictor, respectively? Assume the Branch History Table (BHT) are initialized to the N state. You may assume that this is the only one branch in this program.

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