申論題

3. The execution of an instruction can be divided into five parts: instruction fetch (IF), register
read (RR), ALU operation (EX), data access (MEM), and register write (RW). The following Table 1 shows the execution time of each part for several types of instructions, assuming that the
multiplexors, and control unit have no delay.

If instructions are to be executed in a pipelined CPU with five pipeline stages, IF, RR, EX, MEM,
RW where the pipeline stages execute the corresponding operations mentioned above.