申論題

3. A standard pipelined CPU contains five pipeline stages: instruction fetch (IF), instruction decode (ID), ALU execution (EX), memory access (MA), and result write-back (WB). Assume that the critical path delays of the five types of instruction operations IF, ID, EX, MA, WB are 20ms, 20ns, 50ns, 40ns, 30ns respectively.

3.5 What is super-pipeline? What are the advantages and disadvantages of super-pipeline design?