6.1 Find the AMAT for a processor with a 2 ns clock, a miss penalty of 20 clock cycles, a miss ratc of 0.06 misses per instruction, and a cache access time (including hit detection) of 1 clock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls.

1.3 Consider an architecture that is similar to MIPS except that it supports update addressing for data transfer instructions. If we run SPEC2000int using this architecture, some percentage of the data transfer instructions will be able to make use of the new instructions, and for each instruction changed, one arithmetic instruction can be eliminated. If 25% of the data transfer instructions can be changed, which will be faster for SPEC2000int, the modified MIPS architecture or the unmodified architecture? How much faster? (Assume that both architectures have CPI values as given in the above table and that the modified architecture has its cycle time increased by 20% in order to accommodate the new instructions.)

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6.1 Find the AMAT for a processor with a 2 ns clock, a miss penalty of 20 clock cycles, a miss ratc of 0.06 misses per instruction, and a cache access time (including hit detection) of 1 clock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls.

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