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110年 - 110 國立中山大學碩士暨碩士專班招生考試_通訊所碩士班/甲組:線性代數#104309
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7. (12%) Suppose matrix
. Find a matrix B such that B ● B = A.
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(A)(3%) Compute det(adj(A)).
#441645
(B)(3%) Compute
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(C)(4%) Prove that det= adj(adj(A)).
#441647
9. (12%) . Please compute the QR decomposition of A, where Q is an orthonormal matrix and R is an upper-triangular matrix.
#441648
10.(8%) Find a matrix representation A for the reflection of the plane in the line y = mx. (Hint : Assume that b1 is a Vector which lies along the line y = mx, and b2 is a vector which is orthogonal to b1.)
#441649
2.1 (10%) What is the CPI if this single-core processor only has one level of cache?
#441650
2.2 (20%) To speed up the process, we increase the CPU cores from 1-core CPU to 2-core CPU and retain other design settings. We assume 60% of instructions must be executed sequentially. Please estimate the speedup ratio by using the new architecture.
#441651
3. (20%) Assume a GPU architecture that contains 10 SIMD processors. Each SIMD instruction has a width of 32 and each SIMD process ssor contains 8 lanes for single-precision arithmetic and load/store instructions, meaning that each non-diverged SIMD instruction can produce 32 results every 4 cycles. Assume a kernel that has divergent branches that cause on average 80% of threads to be active. Assume that 70% of all SIMD instructions executed are single-precision arithmetic and 20% are load/store. Since not all memory latencies are covered, assume an average SIMD instruction issue rate of 0.85. Assume that the GPU has a clock speed of 1.5 GHz. Please compute the throughput, in GFLOP/sec, for this kernel on this GPU.
#441652
4.1 (10%) Please determine the number of bits required in the page table, TLB in the L1 cache, and TLB in the L2 cache.
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a. (5%) L1 cache is implemented by using 2-way associative mapping strategy.
#441654
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