5.The latency of a block of digital logic is the time needed to do the work in the block. Assume that logic blocks needed to implement a processor's datapath have the following latencies: Consider the following datapath using the above logic blocks.
申論題內容
(e) What is the clock cycle time if we must support ALU, branch, load/store instructions?
(Hint: You need to find the overall latencies of the blocks in the longest path required to execute an
instruction.)