申論題

3. A standard pipelined CPU contains five pipeline stages: instruction fetch (IF), instruction decode (ID), ALU execution (EX), memory access (MA), and result write-back (WB). Assume that the critical path delays of the five types of instruction operations IF, ID, EX, MA, WB are 20ms, 20ns, 50ns, 40ns, 30ns respectively.

3.3 If we want to reduc ce the pi pipelined stages from 5 to 4 by merging some of the five types of pipelined operations mentioned above, what is the best design if the spced performance is the first choice? And what is the maximun working frequency of the new design with four pipelined stages?