4.2 What would be the actual CPI for the program in Problen 4.1 without forwarding?

4.3 Consider executing the following code on the pipelined datapath of Figure 1. How many cycleswill it take to execute this code?

5.1 Always-taken

5.2 1-bit predictor (initialized to predict taken)

5.3 2-bit predictor as shown in Figure 2 (initialized to weakly predict taken)

6.1 Find the AMAT for a processor with a 2 ns clock, a miss penalty of 20 clock cycles, a miss ratc of 0.06 misses per instruction, and a cache access time (including hit detection) of 1 clock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls.

6.2 Suppose we can improve the miss rate to 0.04 misses per reference by doubling the cache sire. This causes the cache access time to increase to 1.2 clock cycles. Using the AMA'T as a metric, determine if this is a good trade-off.

6.3 If the cache access time determines the processor's clock cycle time, which is often the case, AMAT may not correctly indicate whether one cache organization is better than another. If the processor's clock cycle time must be changed to match that of a cache, is this a good tradc-off? Assume the processors are identical except for the clock rate and the number of cache miss cycles； assume 1.5 references per instruction and a CPI without cache misses of 2. The miss penalty is 20 cycles for both processors.

7.1 Assuming a cache of 16K blocks and a 32-bit address, find the total number of sets and the total number of tag bits for Cache I, Cache 2, and Cache 3.

7.2 Determine which processor spends the most cycles on cache misses.

7.3 The cycle times for the processors in Problem 7.2 are 400 ps for the first and second processors and 300 ps for the third processor. Determine which processor is the fastest and which is the slowest.

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