4.1 We have a program of 1000 instructions in the format of "Iw, add, 1w, add, .. ." The add instruction depends (and only depends) on the 1w instruction right before it. The 1w instruction also depends (and only depends) on the add instruction right before it. If the program is executed on the pipelined datapath of Figure 1, what would be the actual CPI?

1.3 Consider an architecture that is similar to MIPS except that it supports update addressing for data transfer instructions. If we run SPEC2000int using this architecture, some percentage of the data transfer instructions will be able to make use of the new instructions, and for each instruction changed, one arithmetic instruction can be eliminated. If 25% of the data transfer instructions can be changed, which will be faster for SPEC2000int, the modified MIPS architecture or the unmodified architecture? How much faster? (Assume that both architectures have CPI values as given in the above table and that the modified architecture has its cycle time increased by 20% in order to accommodate the new instructions.)

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