38 圖中分別顯示邏輯電路輸出(Output)與輸入(Input)之「1」與「0」狀態的電壓位階範圍,此系 統之「雜訊容限」(Noise margin)NMH及NML為:
(A)NMH = V1-V2,NML = V3-V4
(B)NMH = V6-V2,NML = V3-V7
(C)NMH = V2-V3,NML = V6-V7
(D)NMH = V5-V6,NML = V7-V8

(A)NMH = V1-V2,NML = V3-V4
(B)NMH = V6-V2,NML = V3-V7
(C)NMH = V2-V3,NML = V6-V7
(D)NMH = V5-V6,NML = V7-V8
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統計: A(7), B(65), C(14), D(14), E(0) #814516
統計: A(7), B(65), C(14), D(14), E(0) #814516