6 如圖,CMOS 場效電晶體的輸入端 vI接 VDD時,其輸出端 vo是處於下列何種狀態?
(A)上拉(pull-up)至 VDD
(B)下拉(pull-down)至地
(C)VDD/2
(D)QP與 QN皆關閉,輸出浮接
答案:登入後查看
統計: A(18), B(130), C(24), D(8), E(0) #2354756
統計: A(18), B(130), C(24), D(8), E(0) #2354756